Technical Field
The present disclosure relates to converters and, more particularly, to a control device for quasi-resonant AC/DC flyback converters.
Description of the Related Art
Converters, and particularly offline drivers of LED-based lamps for bulb replacement, are often desired to have a power factor greater than 0.9, low total harmonic distortion (THD) and safety isolation. At the same time, for cost reasons, it is desirable to regulate the output DC current required for proper LED driving without closing a feedback loop. In addition, compatibility with dimmers is becoming more and more important for LED drivers, especially dimmers based on phase-cut technology.
High-power-factor (high-PF) flyback converters are able to meet power factor and isolation specifications with a simple and inexpensive power stage. In a high-PF flyback converter there is not an energy reservoir capacitor directly connected to the input rectifier bridge, so that the voltage applied to the power stage is a rectified sinusoid. To achieve high-PF, the input current tracks the input voltage, thus originating a time-dependent input-to-output power flow. As a result, the output current contains a large AC component at twice the main line's frequency.
A quasi-resonant flyback converter has the power switch turn-on synchronized to the instant the transformer demagnetizes (i.e. the secondary current has become zero), normally after an appropriate delay. This allows the turn-on to occur on the valley of the drain voltage ringing that follows the demagnetization, often termed “valley-switching.” Most commonly, peak current mode control is used, so the turn-off of the power switch is determined by the current sense signal reaching the value programmed by the control loop that regulates the output voltage or current.
In a flyback converter the input current is the average of the primary current, which flows only during the ON-time of the power switch, resulting in a series of triangles separated by voids corresponding to the OFF-time of the power switch. This “chopping” causes the average value of the primary current to be lower than half the peak value and depend on the mark-space ratio of the triangles. As a result, the input current is no longer proportional to the envelope of the peaks and unlike the envelope, which is sinusoidal, the input current is not sinusoidal. Although a sinusoidal-like shape is maintained, the input current is distorted. This distorted sinusoidal input current results in a flyback converter that fails to achieve low THD or unity power factor.
FIG. 1 shows a high-power-factor (high-PF) flyback converter 30 according to the prior art. The hi-PF flyback converter 30 is powered from an AC power line having voltage Vac(θ) and includes an input bridge rectifier 34 having inputs 32 that receive the voltage Vac(θ), a first output connected to ground, and a second output at which the rectifier is configured to produce a rectified sinusoidal voltage Vin(θ)=VPK |sin θ| and the current drawn from the power line is sinusoidal-like.
On the primary side, the flyback converter 30 also comprises a capacitor Cin, which serves as a high-frequency smoothing filter, connected across the output terminals of the bridge rectifier 34, with the negative end connected to ground, and a voltage divider Ra−Rb. The flyback converter 30 has a transformer 36 with a primary winding Lp, connected to the positive terminal of the capacitor Cin, and an auxiliary winding Laux coupled to a resistor RZCD. A power switch M has its drain terminal connected to the primary winding Lp and its source terminal connected to ground via a sense resistor Rs. The current flowing through the power switch M (i.e. the current flowing through the primary winding Lp when M is ON) can be read as a positive voltage drop across the sense resistor Rs. The primary side of the converter also includes a clamp circuit 37 that clamps leakage inductance of the primary winding Lp.
On the secondary side, the transformer 36 includes a secondary winding Ls, that has one end connected to a secondary ground and the other end connected to the anode of a diode D having a cathode connected to the positive plate of a capacitor Cout that has its negative plate connected to the secondary ground.
This flyback converter 30 generates a DC voltage Vout at its output terminals across the capacitor Cout that will supply a load 40, which is a string of high-brightness LEDs in FIG. 1.
The flyback converter has a divider block 42 having a first input that receives a signal B(θ), and a second input that receives a signal A(θ) that is a portion of the instantaneous rectified line voltage sensed across the capacitor Cin and brought to pin MULT through the resistor divider Ra−Rb. The divider ratio Rb/(Ra+Rb) will be denoted with Kp.
The capacitor CT is assumed to be large enough so that the AC component (at twice the line frequency fL) of the signal B(θ) is negligible, at least to a first approximation, with respect to its DC component B0.
The output of the divider block 42 is the division of a rectified sinusoid times a DC level, then still a rectified sinusoid whose amplitude depends on the rms line voltage and the amplitude of the control voltage B0; this will be a reference voltage VcsREF(θ) for the peak primary current.
The signal VcsREF(θ) is fed to the inverting input of a pulse width modulation comparator 44 that receives at its non-inverting input the voltage Vcs(t, θ), sensed across the sense resistor Rs. The voltage Vcs(t, θ) is proportional to the instantaneous current Ip(t, θ) flowing through the primary winding Lp and the power switch M when the switch M is ON. Assuming the power switch M is initially ON, the current through the primary winding Lp will be ramping up and so will the voltage across the sense resistor Rs. When Vcs(t, θ) equals VcsREF(θ), the PWM comparator 44 resets the SR flip-flop 46 which switches off the power switch M. Therefore, the output of the divider 42, shaped as a rectified sinusoid, determines the peak value of the current of the primary winding Lp. As a result, the peak value of the primary winding current will be enveloped by a rectified sinusoid.
After the power switch M has been switched off, the energy stored in the rimary winding Lp is transferred by magnetic coupling to the secondary winding Ls and then dumped into the output capacitor Cout and the load 40 until the secondary winding Ls is completely demagnetized. When the secondary winding Ls is demagnetized, the diode D opens and the drain node becomes floating, which was fixed at Vin(θ)+VR while the secondary winding Ls and the diode D were conducting, with VR being the reflected voltage seen across the primary winding. The voltage at the drain node would tend to eventually reach the instantaneous line voltage Vin(θ) through a damped ringing due to its parasitic capacitance that starts resonating with the primary winding Lp. The quick drain voltage fall that follows the demagnetization of the transformer 36 is coupled to the pin ZCD of the controller through the auxiliary winding Laux and the resistor RZCD. A zero crossing detector (ZCD) block 48 releases a pulse every time it detects a falling edge going below a threshold and this pulse sets the SR flip flop 46 and drives ON the power switch M, starting a new switching cycle.
An OR gate 50 between the ZCD block 48 and the set input of the SR flip flop 46 allows the output of a STARTER block 52 to initiate a switching cycle. The STARTER block outputs a signal at power-on when no signal is available on the input of the ZCD block 48 and prevents the converter from getting stuck in case the signal on the input of the ZCD block 48 is lost for any reason.
The ZCD block 48 also generates a FW signal that is high during transformer's demagnetization, as shown in FIG. 2, and is used by the control loop 56 to generate the B(θ) signal.
Assuming θϵ(0, π), according to the control scheme under consideration the peak envelope of the primary current is given by:Ipkp(θ)=Ip(TON,θ)=IPKp sin θ  (1)
It is worth noticing that this scheme results in a constant ON-time TON of the power switch M:
      T    ON    =            Lp      ⁢                                    I            PKp                    ⁢          sin          ⁢                                          ⁢          θ                                      V            PK                    ⁢          sin          ⁢                                          ⁢          θ                      =          Lp      ⁢                        I          PKp                          V          PK                    
For simplicity, the OFF-time TOFF(θ) of the power switch M will be considered coincident with the time TFW(θ) during which current circulates on the secondary side. In other words, the time interval TR during which the voltage across the power switch M rings (starting just after TFW(θ), as the current in the secondary winding Ls has gone to zero), until reaching the valley of the ringing will be neglected. This is acceptable as long as TR<<TOFF(θ).
The switching period T(θ) is therefore given by:T(θ)=TON+TFW(θ)
Considering volt-second balance across the primary winding Lp it is possible to write:
            T      FW        ⁡          (      θ      )        =            T      ON        ⁢                            V          PK                ⁢        sin        ⁢                                  ⁢        θ                    V        R            
where VR is the reflected voltage, i.e. the output voltage Vout times the primary-to-secondary turns ratio n=Np/Ns, seen across the primary winding Lp of the transformer 36 in the time interval TFW(θ):VR=n(Vout+VF)
where VF is the forward drop on the secondary diode D. Therefore:T(θ)=TON(1+Kv sin θ)
with Kv=VPK/VR.
The input current Iin, to the converter 30 is found by averaging the current Ip(t, θ) in the primary winding Lp over a switching cycle. The current Ip(t, θ) is the series of gray triangles in the right-hand side of FIG. 2 so it is found that:
            I      in        ⁡          (      θ      )        =                    1        2            ⁢                        I          pkp                ⁡                  (          θ          )                    ⁢                        T          ON                          T          ⁡                      (            θ            )                                =                  1        2            ⁢              I        PKp            ⁢                        sin          ⁢                                          ⁢          θ                          1          +                                    K              v                        ⁢            sin            ⁢                                                  ⁢            θ                              
This equation shows that the input current Iin is not a pure sinusoid: this current is sinusoidal only for Kv=0; when Kv≠0, although a sinusoidal-like shape is maintained, the input current is distorted, the higher Kv the higher the distortion. Since Kv cannot be zero (which would require the reflected voltage to tend to infinity), the prior art QR control scheme does not permit zero Total Harmonic Distortion (THD) of the input current nor unity power factor in a flyback converter even in the ideal case.
FIG. 3 shows the plots of the THD of the input current and of the power factor versus Kv.
The regulated DC output current value obtained with this control method is:
      I    out    =            nK      D              2      ⁢              RsG        M            ⁢              R        T            
where KD is the gain of the divider block 42 and GM the transconductance of a current generator 54 which produces current ICH(θ).
This equation shows that with the control method of FIG. 1, which uses only quantities available on its primary side, the DC output current Iout depends only on external, user-selectable parameters (n, Rs) and on internally fixed parameters (GM, RT, KD) and does not depend on the output voltage Vout, nor on the rms input voltage Vin, or the switching frequency fsw(θ)=1/T(θ).
This control method makes the flyback converter 30 work as a current source. Therefore, even with a chopped AC input voltage—which happens in case the converter is operated through a phase-cut wall dimmer (e.g. leading and trailing edge dimmer as shown in FIG. 5)—the converter forces the preset DC output current to the load.
In that case, however it would be desirable to reduce the regulation setpoint depending on the dimmer firing angle (1−α) to be compatible with a dimmer: the higher α is, the lower the current set-point should be. This can be realized by modifying the circuit 56 in FIG. 1 as shown in FIG. 4. The sensed input voltage is compared to a threshold voltage Vth in a dimmer comparator 60 and, if it stays below the threshold for a time longer than TML, it is assumed that the line voltage is missing (because the dimmer is open) and an EN signal goes low. This freezes the state of the power switch M and disconnects both the current generator 54 producing current ICH(θ) and the discharge resistor RT. In this way the voltage across CT is frozen at the value in the instant when the input voltage goes to zero.
The delay TML prevents the circuit from being improperly activated near the zero-crossings of the line voltage when this is not chopped. Note also that this delay is unidirectional: as the sensed voltage exceeds the threshold voltage Vth the enable signal EN goes high immediately.
The net effect of stopping the charge/discharge activity of the capacitor CT can be regarded as an average increase of the discharge resistor RT, leading to a reduction of the preset output current Iout inversely proportion to the firing angle of the dimmer:
      I    out    =                    nK        D                    2        ⁢                  RsG          M                ⁢                  R          T                      ⁢                  (                  1          -          α                )            .      
Real world dimmers have typically a fire angle between 10-20% and 80-90%, and therefore if using the control scheme shown in FIG. 4, the minimum/maximum output current setpoint could be in the range of 10-20% and 80-90% respectively. In other words the control method shown in FIG. 4 cannot meet the typical desired characteristic of a dimmer shown in FIG. 6.